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sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 sn74lvc1g86 single 2-input exclusive-or gate 1 features 3 description the sn74lvc1g86 device performs the boolean 1 ? available in the texas instruments function y = a b or y = ab + a b in positive logic. nanofree ? package this single 2-input exclusive-or gate is designed for ? supports 5-v v cc operation 1.65-v to 5.5-v v cc operation. ? inputs accept voltages to 5.5 v if the input is low, the other input is reproduced in ? supports down translation to v cc true form at the output. if the input is high, the signal ? maximum t pd of 4 ns at 3.3 v and 15-pf load on the other input is reproduced inverted at the output. this device has low power consumption with ? low power consumption, 10- a maximum i cc maximum t pd of 4 ns at 3.3 v and 15-pf capacitive ? 24-ma output drive at 3.3 v load. the max output drive is 32-ma at 4.5 v and ? i off supports live insertion, partial-power-down 24-ma at 3.3 v. mode, and back-drive protection this device is fully specified for partial-power-down ? latch-up performance exceeds 100 ma per applications using i off . the i off circuitry disables the jesd 78, class ii outputs, preventing damaging current back flow through the device when it is powered down. ? esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) device information (1) ? 1000-v charged-device model (c101) part number package body size (nom) sn74lvc1g86dbv sot-23 (5) 2.90 mm 1.60 mm 2 applications sn74lvc1g86dck sc70 (5) 2.00 mm 1.25 mm ? cameras sn74lvc1g86drl sot (5) 1.60 mm 1.20 mm ? programmable logic controllers sn74lvc1g86yzp dsbga (5) 1.44 mm 0.94 mm ? telecom infrastructure (1) for all available packages, see the orderable addendum at ? wireless headsets the end of the data sheet. ? motor drives and controls ? tvs ? set-top boxes ? audio functional block diagram an exclusive-or gate has many applications, some of which can be represented better by alternative logic symbols. these are five equivalent exclusive-or symbols valid for an sn74lvc1g86 gate in positive logic; negation may be shown at any two ports. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. = 1 exclusive or productfolder sample &buy technical documents tools & software support &community
sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 www.ti.com table of contents 8.1 overview ................................................................... 8 1 features .................................................................. 1 8.2 functional block diagram ......................................... 8 2 applications ........................................................... 1 8.3 feature description ................................................... 8 3 description ............................................................. 1 8.4 function table .......................................................... 8 4 revision history ..................................................... 2 9 application and implementation .......................... 9 5 pin configuration and functions ......................... 3 9.1 application information .............................................. 9 6 specifications ......................................................... 4 9.2 typical application ................................................... 9 6.1 absolute maximum ratings ..................................... 4 10 power supply recommendations ..................... 10 6.2 esd ratings .............................................................. 4 11 layout ................................................................... 11 6.3 recommended operating conditions ...................... 4 11.1 layout guidelines ................................................. 11 6.4 thermal information .................................................. 5 11.2 layout example .................................................... 11 6.5 electrical characteristics ........................................... 5 12 device and documentation support ................. 12 6.6 switching characteristics, c l = 15 pf ...................... 6 12.1 community resources .......................................... 12 6.7 switching characteristics, c l = 30 pf or 50 pf ........ 6 12.2 trademarks ........................................................... 12 6.8 operating characteristics .......................................... 6 12.3 electrostatic discharge caution ............................ 12 6.9 typical characteristics .............................................. 6 12.4 glossary ................................................................ 12 7 parameter measurement information .................. 7 13 mechanical, packaging, and orderable 8 detailed description .............................................. 8 information ........................................................... 12 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision o (december 2013) to revision p page ? added applications section, device information table, esd ratings table, thermal information table, typical characteristics section, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ................................................................................................. 1 ? ................................................................................................................................................................................................ 5 changes from revision n (january 2007) to revision o page ? updated document to new ti data sheet format. ................................................................................................................... 1 ? removed ordering information table. .................................................................................................................................... 1 ? updated i off in features . ......................................................................................................................................................... 1 ? updated operating temperature range. .................................................................................................................................. 4 2 submit documentation feedback copyright ? 1999 ? 2015, texas instruments incorporated product folder links: sn74lvc1g86
sn74lvc1g86 www.ti.com sces222p ? april 1999 ? revised september 2015 5 pin configuration and functions dbv package dck package 5-pin sot-23 5-pin sc70 top view top view yzp package 5-pin dsbga bottom view drl package 5-pin sot top view pin functions (1) pin i/o description no. name 1 a i input a 2 b i input b 3 gnd ? ground pin 4 y o output y 5 v cc ? power pin (1) see mecahnical drawings for dimensions. copyright ? 1999 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: sn74lvc1g86 2 b v cc 5 1 a 3 4 gnd gnd y 2 b v cc 1 5 a gnd 4 3 y 5 1 v cc a 2 b 3 4 gnd y 2 b 3 4 gnd v cc 5 a y 1
sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 6.5 v v i input voltage (2) ? 0.5 6.5 v v o voltage applied to any output in the high-impedance or power-off state (2) ? 0.5 6.5 v v o voltage applied to any output in the high or low state (2) (3) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma t j junction temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 electrostatic v (esd) v discharge charged-device model (cdm), per jedec specification jesd22-c101, all pins (2) 1000 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit operating 1.65 5.5 v cc supply voltage v data retention only 1.5 v cc = 1.65 v to 1.95 v 0.65 v cc v cc = 2.3 v to 2.7 v 1.7 v ih high-level input voltage v v cc = 3 v to 3.6 v 2 v cc = 4.5 v to 5.5 v 0.7 v cc v cc = 1.65 v to 1.95 v 0.35 v cc v cc = 2.3 v to 2.7 v 0.7 v il low-level input voltage v v cc = 3 v to 3.6 v 0.8 v cc = 4.5 v to 5.5 v 0.3 v cc v i input voltage 0 5.5 v v o output voltage 0 v cc v v cc = 1.65 v ? 4 v cc = 2.3 v ? 8 i oh high-level output current ? 16 ma v cc = 3 v ? 24 v cc = 4.5 v ? 32 (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004 . 4 submit documentation feedback copyright ? 1999 ? 2015, texas instruments incorporated product folder links: sn74lvc1g86
sn74lvc1g86 www.ti.com sces222p ? april 1999 ? revised september 2015 recommended operating conditions (continued) over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc = 1.65 v 4 v cc = 2.3 v 8 i ol low-level output current 16 ma v cc = 3 v 24 v cc = 4.5 v 32 v cc = 1.8 v 0.15 v, 2.5 v 0.2 v 20 t/ input transition rise or fall rate v cc = 3.3 v 0.3 v 10 ns/v v v cc = 5 v 0.5 v 5 yzp package ? 40 85 t a operating free-air temperature c dck, dbv, and drl packages ? 40 125 6.4 thermal information sn74lvc1g86 thermal metric (1) dbv (sot-23) dck (sc70) yzp (dsbga) unit 5 pins 5 pins 5 pins r ja junction-to-ambient thermal resistance 206 252 132 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit i oh = ? 100 a 1.65 v to 5.5 v v cc ? 0.1 i oh = ? 4 ma 1.65 v 1.2 i oh = ? 8 ma 2.3 v 1.9 v oh v i oh = ? 16 ma 2.4 3 v i oh = ? 24 ma 2.3 i oh = ? 32 ma 4.5 v 3.8 i ol = 100 a 1.65 v to 5.5 v 0.1 i ol = 4 ma 1.65 v 0.45 i ol = 8 ma 2.3 v 0.3 v ol v i ol = 16 ma 0.4 3 v i ol = 24 ma 0.55 i ol = 32 ma 4.5 v 0.55 i i a or b input v i = 5.5 v or gnd 0 to 5.5 v 5 a i off v i or v o = 5.5 v 0 10 a ? 40 c to 85 c 10 i cc v i = v cc or gnd, i o = 0 1.65 v to 5.5 v a ? 40 c to 125 c 15 one input at v cc ? 0.6 v, i cc 3 v to 5.5 v 500 a other inputs at v cc or gnd c i v i = v cc or gnd ? 40 c to 85 c temp range 3.3 v 6 pf (1) all typical values are at v cc = 3.3 v, t a = 25 c. copyright ? 1999 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: sn74lvc1g86
sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 www.ti.com 6.6 switching characteristics, c l = 15 pf over recommended operating free-air temperature range (unless otherwise noted) (see figure 2 ) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v paramete from to 0.15 v 0.2 v 0.3 v 0.5 v test conditions unit r (input) (output) min max min max min max min max t pd a or b y ? 40 c to 85 c temp range 2.1 9.1 1 4.5 0.6 4 0.8 3.3 ns 6.7 switching characteristics, c l = 30 pf or 50 pf over recommended operating free-air temperature range (unless otherwise noted) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v from to 0.15 v 0.2 v 0.3 v 0.5 v parameter test conditions unit (input) (output) min max min max min max min max ? 40 c to 85 c temp range, 3.5 9.9 1.8 5.5 1.3 5 1 4 see figure 2 t pd a or b y ns ? 40 c to 125 c temp range, 3.5 12 1.8 7 1.3 6 1 5 see figure 2 6.8 operating characteristics t a = 25 c v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v parameter test conditions unit typ typ typ typ c pd power dissipation capacitance f = 10 mhz 22 22 22 24 pf 6.9 typical characteristics figure 1. v oh vs i oh at 4.5 v 6 submit documentation feedback copyright ? 1999 ? 2015, texas instruments incorporated product folder links: sn74lvc1g86 v oh (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.5 -1 i oh (ma) 0 20 40 60 80 100 120 140 160 180 200 v cc =4.5 v v ih =3.1 v v il =1.35 v 85 o c -40 o c 25 o c
sn74lvc1g86 www.ti.com sces222p ? april 1999 ? revised september 2015 7 parameter measurement information figure 2. load circuit and voltage waveforms copyright ? 1999 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: sn74lvc1g86 t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v? 0 v outputoutput t /t plh phl open test s1 output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 m 1 m 1 m 1 m v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 15 pf15 pf 15 pf 15 pf 0.15 v0.15 v 0.3 v0.3 v v d 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc v load t /t plz pzl gnd t /t phz pzh voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. t and t are the same as t . f. t and t are the same as t . g. t and t are the same as t . h. all parameters and waveforms are not applicable to all devices. l o plz phz dis pzl pzh en plh phl pd voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh d v + v ol d v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl
sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 www.ti.com 8 detailed description 8.1 overview the sn74lvc1g86 device performs the boolean function y = a b or y = ab + a b in positive logic. this single 2-input exclusive-or gate is designed for 1.65-v to 5.5-v v cc operation. a common application is as a true/complement element. if the input is low, the other input is reproduced in true form at the output. if the input is high, the signal on the other input is reproduced inverted at the output. nanofree package technology is a major breakthrough in ic packaging concepts, using the die as the package. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 functional block diagram these are five equivalent exclusive-or symbols valid for an sn74lvc1g86 gate in positive logic; negation may be shown at any two ports. 8.3 feature description sn74lvc1g86 has a wide operating voltage range from 1.65 v to 5.5 v.this allows down voltage translation and also accepts inputs voltages to 5.5 v. the maximum propagation delay is 4n s at 3.3 v at 15-pf capacitor load. power consumption is low with 10 a maximum i cc current. it supports 24-ma output drive at 3.3 v. the sn74lvc1g86 is specified for partial power down applications using i off supporting live insertion and back-drive protection. 8.4 function table table 1 lists the functional modes of the sn74lvc1g86. table 1. function table inputs output y a b l l l l h h h l h h h l 8 submit documentation feedback copyright ? 1999 ? 2015, texas instruments incorporated product folder links: sn74lvc1g86 = 1 exclusive or
sn74lvc1g86 www.ti.com sces222p ? april 1999 ? revised september 2015 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information sn74lvc1g86 can accept input voltages to 5.5 v at any valid v cc which makes it suitable for down translation. this feature of sn74lvc1g86 makes it ideal for various bus interface applications. 9.2 typical application figure 3. typical application schematic 9.2.1 design requirements this device uses cmos technology and has balanced output drive. take care to avoid bus contention because it can drive currents that would exceed maximum limits. the high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 9.2.2 detailed design procedure 1. recommended input conditions ? for rise time and fall time specifications, see t/ v in the recommended operating conditions table. ? for specified high and low levels, see v ih and v il in the recommended operating conditions table. ? inputs are overvoltage tolerant allowing them to go as high as 5.5 v at any valid v cc . 2. recommend output conditions ? load currents should not exceed 32 ma per output and 50 ma total for the part. ? outputs should not be pulled above v cc . copyright ? 1999 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: sn74lvc1g86 3.3-v or 5-v regulated 0.1 f 5-v accessory 5-v system logic c or system logic
sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 www.ti.com typical application (continued) 9.2.3 application curve figure 4. icc vs. vin 10 power supply recommendations the power supply can be any voltage between the minimum and maximum supply voltage rating located in the recommended operating conditions table. each v cc pin should have a good bypass capacitor to prevent power disturbance. for devices with a single supply, 0.1 f is recommended. if there are multiple v cc pins, 0.01 f or 0.022 f is recommended for each power pin. it is acceptable to parallel multiple bypass caps to reject different frequencies of noise. a 0.1- f and 1- f are commonly used in parallel. the bypass capacitor should be installed as close to the power pin as possible for best results. 10 submit documentation feedback copyright ? 1999 ? 2015, texas instruments incorporated product folder links: sn74lvc1g86 i cc (ma) v in (v) 0 10 20 0.5 0 30 40 50 60 70 80 90 100 1.5 1 2.5 2 3.5 3 6 5.5 4 5 4.5 v ih = 4.5v v il = 0v v cc = 5.5v temp =25 o c low->high high->low
sn74lvc1g86 www.ti.com sces222p ? april 1999 ? revised september 2015 11 layout 11.1 layout guidelines when using multiple bit logic devices, inputs should not float. in many cases, functions or parts of functions of digital logic devices are unused. some examples are when only two inputs of a triple-input and gate are used, or when only 3 of the 4-buffer gates are used. such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. specified in figure 5 are rules that must be observed under all circumstances. all unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. the logic level that should be applied to any particular unused input depends on the function of the device. generally they will be tied to gnd or v cc , whichever makes more sense or is more convenient. it is acceptable to float outputs unless the part is a transceiver. if the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. this will not disable the input section of the i/os so they also cannot float when disabled. 11.2 layout example figure 5. layout diagram copyright ? 1999 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: sn74lvc1g86 v cc unused input input output input unused input output
sn74lvc1g86 sces222p ? april 1999 ? revised september 2015 www.ti.com 12 device and documentation support 12.1 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.2 trademarks nanofree, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 12 submit documentation feedback copyright ? 1999 ? 2015, texas instruments incorporated product folder links: sn74lvc1g86
package option addendum www.ti.com 5-dec-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn74lvc1g86dbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (c865 ~ c86f ~ c86k ~ c86r) sn74lvc1g86dbvre4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c86f sn74lvc1g86dbvrg4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c86f sn74lvc1g86dbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (c865 ~ c86f ~ c86k ~ c86r) sn74lvc1g86dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch5 ~ chf ~ chk ~ chr) SN74LVC1G86DCKRE4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch5 ~ chf ~ chk ~ chr) sn74lvc1g86dckrg4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch5 ~ chf ~ chk ~ chr) sn74lvc1g86dckt active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch5 ~ chf ~ chk ~ chr) sn74lvc1g86dcktg4 active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch5 ~ chf ~ chk ~ chr) sn74lvc1g86drlr active sot drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch7 ~ chr) sn74lvc1g86drlrg4 active sot drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ch7 ~ chr) sn74lvc1g86yzpr active dsbga yzp 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 (ch7 ~ chn) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 5-dec-2015 addendum-page 2 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn74lvc1g86 : ? enhanced product: sn74lvc1g86-ep note: qualified version definitions: ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74lvc1g86dbvr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g86dbvr sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g86dbvr sot-23 dbv 5 3000 180.0 9.2 3.17 3.23 1.37 4.0 8.0 q3 sn74lvc1g86dbvrg4 sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g86dbvt sot-23 dbv 5 250 180.0 9.2 3.17 3.23 1.37 4.0 8.0 q3 sn74lvc1g86dbvt sot-23 dbv 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g86dckr sc70 dck 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74lvc1g86dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lvc1g86dckr sc70 dck 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74lvc1g86dckt sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lvc1g86dckt sc70 dck 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74lvc1g86dckt sc70 dck 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74lvc1g86drlr sot drl 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 sn74lvc1g86drlr sot drl 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 q3 sn74lvc1g86yzpr dsbga yzp 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 q1 package materials information www.ti.com 18-jan-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74lvc1g86dbvr sot-23 dbv 5 3000 202.0 201.0 28.0 sn74lvc1g86dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lvc1g86dbvr sot-23 dbv 5 3000 205.0 200.0 33.0 sn74lvc1g86dbvrg4 sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lvc1g86dbvt sot-23 dbv 5 250 205.0 200.0 33.0 sn74lvc1g86dbvt sot-23 dbv 5 250 180.0 180.0 18.0 sn74lvc1g86dckr sc70 dck 5 3000 205.0 200.0 33.0 sn74lvc1g86dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74lvc1g86dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74lvc1g86dckt sc70 dck 5 250 180.0 180.0 18.0 sn74lvc1g86dckt sc70 dck 5 250 205.0 200.0 33.0 sn74lvc1g86dckt sc70 dck 5 250 180.0 180.0 18.0 sn74lvc1g86drlr sot drl 5 4000 202.0 201.0 28.0 sn74lvc1g86drlr sot drl 5 4000 184.0 184.0 19.0 sn74lvc1g86yzpr dsbga yzp 5 3000 220.0 220.0 35.0 package materials information www.ti.com 18-jan-2016 pack materials-page 2

d: max = e: max = 1.44 mm, min = 0.94 mm, min = 1.38 mm0.88 mm
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